[ SYSTEM BOOT ]
LOADING
ACQUIRING SIGNAL
Two equal resistors in series between +5 V and ground, with the output tap at their junction. Classic 2:1 voltage divider.
| REF | TYPE | VALUE | ROLE |
|---|---|---|---|
| R1 | Resistor | 10 kΩ | Upper (series) resistor of the divider — sets the source impedance seen by the load and, together with R2, the divide ratio. |
| R2 | Resistor | 10 kΩ | Lower (shunt) resistor to ground — fixes the output node voltage at Vin × R2 / (R1 + R2). |
| VIN | Voltage source | +5 V | Reference rail being divided down. |
| VOUT | Net / probe point | — | Tap point between R1 and R2 — feeds the downstream high-impedance load (ADC, op-amp input, comparator). |
4 COMPONENTS IDENTIFIED
STAGES · 3
Reference rail
Stiff DC source supplies current into the series resistor.
→ VIN
Series element
R1 carries the divider current to the tap node.
→ R1
Shunt element
R2 sinks the divider current to ground, fixing the tap voltage.
→ R2
FEEDBACK PATHS
No feedback — open-loop passive network. Output depends entirely on the divider ratio and the impedance of the downstream load.
KEY NODES
DOMAIN
signal processing
INDUSTRY
Universal — appears in every analog front end ever designed. The first building block in any electronics curriculum and the unsung hero of bandgap references, level translators, and feedback networks.
FREQUENCY
DC to ~1 MHz (limited by stray capacitance at the tap node)
IMPEDANCE
Source impedance at VOUT = R1 ∥ R2 = 5 kΩ
APPLICATION
Reference / bias generation. Used to derive a stable mid-rail voltage, scale a signal into an ADC range, or set a bias point for a transistor or op-amp.
OPERATING PRINCIPLE
Two resistors in series form a current path from Vin to ground; the voltage at their midpoint equals the input scaled by the ratio R2 / (R1 + R2). With R1 = R2, the output is exactly Vin / 2. The divider only behaves ideally when the load impedance is much larger than the parallel combination of R1 and R2 — otherwise the load draws current that pulls the tap voltage down and changes the effective ratio.
KEY PARAMETERS
Divide ratio
0.5
R2 / (R1 + R2) — output is half the input
Vout (no load)
2.5V
Source impedance
5kΩ
R1 in parallel with R2
Quiescent current
250µA
5 V / 20 kΩ — wasted as heat in the divider
Bandwidth limit
~3MHz
Approximate, set by ~10 pF of stray capacitance
DESIGN DECISIONS
Choosing 10 kΩ for both resistors is the standard compromise between two competing failures: too small and you waste current (1 kΩ each would burn 2.5 mA continuously); too large and the source impedance starts to interact with ADC sampling capacitors, op-amp input bias currents, and stray PCB capacitance. 10 kΩ keeps the bleed current under a quarter milliamp while staying comfortably below the ~100 kΩ region where leakage and op-amp bias currents start to dominate. Using 1% metal-film resistors keeps the ratio error under ~1.4% worst case.
FAILURE MODES · 3
Loading the output with a low-impedance device
If the downstream stage has input impedance comparable to 5 kΩ (e.g. a bipolar op-amp's bias current path, or a relay coil), the tap voltage sags and the divide ratio is no longer R2 / (R1 + R2). The output collapses toward ground.
Driving a switching capacitive load (ADC SAR)
An ADC's sample-and-hold capacitor wants to charge through the 5 kΩ source impedance every conversion. If the ADC's acquisition time is shorter than ~5 × R × C_sample, the divider can't keep up and the reading is wrong.
Resistor tolerance stack-up
5% carbon-film resistors can give a divide ratio anywhere from 0.476 to 0.526 in the worst case — enough error to matter for any precision application.
IMPROVEMENT SUGGESTIONS
◇ Buffering
Add a unity-gain op-amp buffer (e.g. OPA340) between the tap and the load.
Drops the effective source impedance from 5 kΩ to a few milliohms, isolating the divider from anything the load does. Essential if the load is variable or capacitive.
◇ Bypass capacitor
Place a 100 nF ceramic from VOUT to ground.
Filters high-frequency noise on the input rail and gives ADC sample-and-hold circuits a local charge reservoir, fixing the acquisition-time problem above.
◇ Precision
Use a single matched resistor network (e.g. Vishay MORN, 0.1% ratio match) instead of two discrete resistors.
Ratio accuracy goes from ~1.4% to ~0.1%, and temperature drift tracks because both elements are on the same die.
[ END OF ANALYSIS ]
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